In recent years, an interconnect structure of a semiconductor device has been formed by combining interconnects and air gaps in many cases to prevent increase of capacitance between the interconnects due to miniaturization of the semiconductor device. Such an interconnect structure is generally formed in the following manner. First, a conductive film is formed, and is processed by reactive ion etching (RIE) to form a plurality of interconnects from the conductive film. Next, an insulator that is inferior in filling properties is formed on these interconnects. As a result, when a distance between the interconnects is short, the insulator fails to fill gaps between the interconnects, so that the air gaps are formed between the interconnects. In general, upper portions of the air gaps become acicular shapes.
In the interconnect structure having the air gaps, the mechanical vulnerability of the semiconductor device becomes a problem. For example, shear stress acts on the interconnect structure in a chemical mechanical polishing (CMP) process performed to planarize a film on the interconnect structure. Accordingly, cracks may be generated from the acicular upper portions of the air gaps so as to cause damage to the interconnect structure. This is also true for forces acting on the interconnect structure under other situations.